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NCTU EE | Github : mirkat1206 | mirkat.ding@gmail.com

單純記錄一下自己的肝都用在哪裡

I don’t own the rights of this picture, see link.

課程資料

積體電路設計實驗 Integrated Circuit Design Laboratory
教授:李鎮宜
修課年度:109下 電子碩(大四下)
GitHub: 2021_Spring_NCTU_ICLAB

需要的基礎

邏輯設計、數位電路與系統、電子學(一)超大型積體電路設計導論VLSI

課程大綱

詳細上課內容可以參考連結。

Lec00: Develop Environme …


單純記錄一下自己的肝都用在哪裡

I don’t own the rights of this picture, see link.

課程資料

資料結構 Data Structures
教授:黃俊達
修課年度:107上 電工系(大二上)
教科書:Fundamentals of Data Structures in C++ 2/e
我的額外參考書:打下好基礎:程式設計與演算法競賽入門經典
額外參考書勘誤整理:程式設計與演算法競賽入門經典_勘誤
GitHub: NCTUEE/1071_Data_Structure/

需要的基礎

程式設計﹑C++。

課程大綱

chapter 1:Basics
chapter 2:Arrays
chapter 3:Stacks and Queues
chapter 4:Linked Lists
chapter 5:Trees
chapter 6:Graphs
chapter 7:Sorting
chapter 8:Hashing

上課方式

上課以投影片為主。老師依照投影片的內容仔細講解,並加以補充。

阿達老師是位非常有教學熱忱的老師,個人認為他教的非常好,無論是觀念或是程式碼,都講解的十分清楚。不過老師對於『考古題』這件事十分在乎,通常考卷分數確定沒問題後,就會被收回去,不太有機會留傳給學弟妹。

我習慣將講義印出來,跟著老師的進度作筆記,之後複習比較有印象。

阿達老師的課真的很熱門,當初修這堂課的時候工四大教室被塞得滿滿滿的,開學第一堂課老師還努力勸退一些人不要修,不然教室要塞不下啦🙃。

評分方式

Attendance:10%
Programming Assignments:30%
Midterm:30%
Final:30%

作業

GitHub: NCTUEE/1071_Data_Structure/

HW1:Prime Checker
HW2:走迷宮問題
HW3:以 List 實現多項式
HW4:實作 Binary Search Tree
HW5:Graph

最後一次作業比較燒腦,助教說並沒有所謂的最佳解,我自己設計了一套演算法去優化。不過最後排名出來時,前幾名的performance都差不多,可見應該還是有一些比較好的方法來解這個最短路徑的問題。

考試

年代久遠,已經忘記☹️。不過應該是有讀有分的考試。

心得

關於這門課,我個人的學習曲線跟大家應該不太一樣。

大一下時已經修過離散數學﹑物件導向程式設計:大二上時,我同時修了資料結構(大二課程)與演算法(大三課程)。本門課的內容前半部與離散數學﹑物件導向程式設計重疊﹑後半部則是演算法前半部課程的簡化版;再加上我高中時就有參加資訊能力競賽的經驗,除了 chapter 8:Hashing 以外,其他章節高中都有稍微接觸過。因此這門課對我來說挺輕鬆的。

讀書方式是將離散數學、資料結構、演算法三科講義交叉閱讀(我很幸運,這三科都是修阿達老師所開的課),並搭配打下好基礎:程式設計與演算法競賽入門經典一起學習。打下好基礎:程式設計與演算法競賽入門經典是由中國的劉汝佳老師所撰寫,內容從程式基礎(語言篇)、資料結構(基礎篇)、到演算法(競賽篇)都有涵蓋。

如同書名,此書是高中準備資訊能力競賽時所購買的,但高中時只讀到語言篇。到了大二修資料結構、演算法時,才又重新將此書拿出來。這時才發現這本書完全不愧對「入門經典」這個書名,上課內容都有對應的章節可以閱讀,且提供豐富的範例及UVa例題讓讀者理解及練習,剛好可以跟上課講義互補缺漏。

程式設計與演算法競賽入門經典_勘誤是我大二時閱讀此書所做的勘誤筆記整理,但一直拖到今年才將筆記整理成檔案寄信給出版社。很可惜的得知此書已經不再出版,不然很推薦大家購買此書搭配課程學習。收到出版社的感謝信真的很開心,希望台灣還能再出版劉汝佳老師的書籍。


Week 15

LAB Description

Topic of this week

  1. Power Verification
  2. Bonding Pads Insertion Flow
  3. Cell-Based Design Flow Review

Design

Artificial Neural Network APRII

Description

Finish the backend flow (APR) for the finished design and do the power verification.

GitHub

2021_Spring_NCTU_ICLAB/Lab12/

What did I learn?

  1. How to do Power Analysis with Cadence Innovus.
  2. More power stripes, less IR drop.

Lecture Note

Power Component


Week 14

LAB Description

Topic of this week

  1. What is APR
  2. SOP of APR

Design

Matrix Computation (MC)

Description

Run the APR flow and post-simulation for the finished design MC.

GitHub

2021_Spring_NCTU_ICLAB/Lab11/

What did I learn?

  1. Review Cell-based Design Flow
  2. How to do APR with Cadence Innovus.

Lecture Note

Cell-based Design Flow

  1. Specification Development, System Models.
  2. RTL Code Development, Function Verification.
  3. Synthesis, Timing Verification.
  4. Physical Synthesis & Place & Route…


Week 13

LAB Description

Topic of this week

  1. Introduction to Formal Analysis
  2. Introduction to SVA
  3. JasperGold — Setup / Formal Coverage Analysis / Assertion Based Verification IP & Scoreboard
  4. Bound Analysis

Design

Formal Verification

Description

Use ABCIP to verify the offered Customized I/O to AXI4-Lite bridge with build-in scoreboard and customized SVA by Formal Verification tool — JasperGold.

What did I learn?

  1. Concepts of…

Week 12

LAB Description

I don’t own the rights of this picture.

Topic of this week

  1. Functional Coverage
  2. Assertion

Design

Coverage of Lab09 Happy Farm (HF)

Description

Write the verification pattern for Lab09 HF and achieve coverage goals.

GitHub

2021_Spring_NCTU_ICLAB/Lab10/

What did I learn?

  1. How to write assertions using SystemVerilog.
  2. How to calculate different coverage.

Reference Link

SystemVerilog Assertions Basics
SystemVerilog Assertions Tutorial
SV — Coverage 覆盖率
SV之覆盖率

上一篇:ICLAB Lab09 Note
下一篇:ICLAB Bonus Lab Note


Week 11

LAB Description

Topic of this week

  1. Introduction to SystemVerilog
  2. Design Using SystemVerilog
  3. Verification Using SystemVerilog

Design

Happy Farm (HF)

Description

Build a well-known game called Happy Farm with several operations and different crops in SystemVerilog.

GitHub

2021_Spring_NCTU_ICLAB/Lab09/

What did I learn?

  1. Basic of SystemVerilog.
  2. Different usage of SystemVerilog from Verilog.
  3. Different specs may result in different performance with same design.

SystemVerilog Note

SystemVerilog is a…


Week 10

LAB Description

Topic of this week

  1. Power Dissipation
  2. Low Power Design Introduction
  3. Static Power Reduction
  4. Dynamic Power Reduction

Design

Series Processiong (SP)

Description

Do three operations (Modular Inversion / Modular Multiplication / Sorting / Sum ) according to different mode signal.

GitHub

2021_Spring_NCTU_ICLAB/Lab08/

What did I learn?

  1. How to use gated-clock to reduce power.
  2. How to use JasperGold.
  3. Think thoroughly before trying to…

Week 9

LAB Description

Topic of this week

  1. Timing Analysis Considering Clock Latency
  2. Multicycle Path Specification
  3. Clock Domain Crossing (CDC)

Design

Polish Notation (PN)

Description

Calculate the answers of arithmetic expressions in the forms of prefix or postfix expression with 3 clock domains.

GitHub

2021_Spring_NCTU_ICLAB/Lab07/

What did I learn?

  1. What are infix/prefix/postfix expression.
  2. How to realize CDC solution : Double Flip-Flop Synchronizer.

Lecture Note

Static Timing Analysis, STA

What is Static…


Week 7

LAB Description

Topic of this week

  1. Design Compiler Introduction
  2. Basic Synthesis Flow
  3. Generate & For Loop

Design

CheckSum (CS)

Description

First design a checksum soft IP which can calculate the checksum of the input data. Second design a processor which contains 2 checksum IPs.

GitHub

2021_Spring_NCTU_ICLAB/Lab06/

What did I learn?

  1. How to create soft IP.
  2. Basic of .tcl (Tool Command Language) files.
  3. Usage…

Mirkat

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